check in v3.8.2 source
This commit is contained in:
412
crypto/modes/ghash-elf-armv4.S
Normal file
412
crypto/modes/ghash-elf-armv4.S
Normal file
@@ -0,0 +1,412 @@
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#include "arm_arch.h"
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.text
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.syntax unified
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.code 32
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.type rem_4bit,%object
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.align 5
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rem_4bit:
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.short 0x0000,0x1C20,0x3840,0x2460
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.short 0x7080,0x6CA0,0x48C0,0x54E0
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.short 0xE100,0xFD20,0xD940,0xC560
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.short 0x9180,0x8DA0,0xA9C0,0xB5E0
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.size rem_4bit,.-rem_4bit
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.type rem_4bit_get,%function
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rem_4bit_get:
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sub r2,pc,#8
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sub r2,r2,#32 @ &rem_4bit
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b .Lrem_4bit_got
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nop
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.size rem_4bit_get,.-rem_4bit_get
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.global gcm_ghash_4bit
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.type gcm_ghash_4bit,%function
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gcm_ghash_4bit:
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sub r12,pc,#8
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add r3,r2,r3 @ r3 to point at the end
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stmdb sp!,{r3-r11,lr} @ save r3/end too
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sub r12,r12,#48 @ &rem_4bit
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ldmia r12,{r4-r11} @ copy rem_4bit ...
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stmdb sp!,{r4-r11} @ ... to stack
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ldrb r12,[r2,#15]
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ldrb r14,[r0,#15]
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.Louter:
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eor r12,r12,r14
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and r14,r12,#0xf0
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and r12,r12,#0x0f
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mov r3,#14
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add r7,r1,r12,lsl#4
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ldmia r7,{r4-r7} @ load Htbl[nlo]
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add r11,r1,r14
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ldrb r12,[r2,#14]
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and r14,r4,#0xf @ rem
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ldmia r11,{r8-r11} @ load Htbl[nhi]
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add r14,r14,r14
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eor r4,r8,r4,lsr#4
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ldrh r8,[sp,r14] @ rem_4bit[rem]
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eor r4,r4,r5,lsl#28
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ldrb r14,[r0,#14]
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eor r5,r9,r5,lsr#4
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eor r5,r5,r6,lsl#28
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eor r6,r10,r6,lsr#4
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eor r6,r6,r7,lsl#28
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eor r7,r11,r7,lsr#4
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eor r12,r12,r14
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and r14,r12,#0xf0
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and r12,r12,#0x0f
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eor r7,r7,r8,lsl#16
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.Linner:
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add r11,r1,r12,lsl#4
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and r12,r4,#0xf @ rem
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subs r3,r3,#1
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add r12,r12,r12
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ldmia r11,{r8-r11} @ load Htbl[nlo]
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eor r4,r8,r4,lsr#4
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eor r4,r4,r5,lsl#28
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eor r5,r9,r5,lsr#4
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eor r5,r5,r6,lsl#28
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ldrh r8,[sp,r12] @ rem_4bit[rem]
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eor r6,r10,r6,lsr#4
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ldrbpl r12,[r2,r3]
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eor r6,r6,r7,lsl#28
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eor r7,r11,r7,lsr#4
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add r11,r1,r14
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and r14,r4,#0xf @ rem
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eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
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add r14,r14,r14
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ldmia r11,{r8-r11} @ load Htbl[nhi]
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eor r4,r8,r4,lsr#4
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ldrbpl r8,[r0,r3]
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eor r4,r4,r5,lsl#28
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eor r5,r9,r5,lsr#4
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ldrh r9,[sp,r14]
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eor r5,r5,r6,lsl#28
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eor r6,r10,r6,lsr#4
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eor r6,r6,r7,lsl#28
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eorpl r12,r12,r8
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eor r7,r11,r7,lsr#4
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andpl r14,r12,#0xf0
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andpl r12,r12,#0x0f
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eor r7,r7,r9,lsl#16 @ ^= rem_4bit[rem]
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bpl .Linner
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ldr r3,[sp,#32] @ re-load r3/end
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add r2,r2,#16
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mov r14,r4
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r4,r4
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str r4,[r0,#12]
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#elif defined(__ARMEB__)
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str r4,[r0,#12]
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#else
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mov r9,r4,lsr#8
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strb r4,[r0,#12+3]
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mov r10,r4,lsr#16
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strb r9,[r0,#12+2]
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mov r11,r4,lsr#24
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strb r10,[r0,#12+1]
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strb r11,[r0,#12]
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#endif
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cmp r2,r3
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r5,r5
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str r5,[r0,#8]
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#elif defined(__ARMEB__)
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str r5,[r0,#8]
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#else
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mov r9,r5,lsr#8
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strb r5,[r0,#8+3]
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mov r10,r5,lsr#16
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strb r9,[r0,#8+2]
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mov r11,r5,lsr#24
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strb r10,[r0,#8+1]
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strb r11,[r0,#8]
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#endif
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ldrbne r12,[r2,#15]
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r6,r6
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str r6,[r0,#4]
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#elif defined(__ARMEB__)
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str r6,[r0,#4]
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#else
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mov r9,r6,lsr#8
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strb r6,[r0,#4+3]
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mov r10,r6,lsr#16
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strb r9,[r0,#4+2]
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mov r11,r6,lsr#24
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strb r10,[r0,#4+1]
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strb r11,[r0,#4]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r7,r7
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str r7,[r0,#0]
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#elif defined(__ARMEB__)
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str r7,[r0,#0]
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#else
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mov r9,r7,lsr#8
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strb r7,[r0,#0+3]
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mov r10,r7,lsr#16
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strb r9,[r0,#0+2]
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mov r11,r7,lsr#24
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strb r10,[r0,#0+1]
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strb r11,[r0,#0]
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#endif
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bne .Louter
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add sp,sp,#36
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r11,pc}
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#else
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ldmia sp!,{r4-r11,lr}
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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#endif
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.size gcm_ghash_4bit,.-gcm_ghash_4bit
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.global gcm_gmult_4bit
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.type gcm_gmult_4bit,%function
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gcm_gmult_4bit:
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stmdb sp!,{r4-r11,lr}
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ldrb r12,[r0,#15]
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b rem_4bit_get
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.Lrem_4bit_got:
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and r14,r12,#0xf0
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and r12,r12,#0x0f
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mov r3,#14
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add r7,r1,r12,lsl#4
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ldmia r7,{r4-r7} @ load Htbl[nlo]
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ldrb r12,[r0,#14]
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add r11,r1,r14
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and r14,r4,#0xf @ rem
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ldmia r11,{r8-r11} @ load Htbl[nhi]
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add r14,r14,r14
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eor r4,r8,r4,lsr#4
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ldrh r8,[r2,r14] @ rem_4bit[rem]
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eor r4,r4,r5,lsl#28
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eor r5,r9,r5,lsr#4
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eor r5,r5,r6,lsl#28
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eor r6,r10,r6,lsr#4
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eor r6,r6,r7,lsl#28
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eor r7,r11,r7,lsr#4
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and r14,r12,#0xf0
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eor r7,r7,r8,lsl#16
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and r12,r12,#0x0f
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.Loop:
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add r11,r1,r12,lsl#4
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and r12,r4,#0xf @ rem
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subs r3,r3,#1
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add r12,r12,r12
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ldmia r11,{r8-r11} @ load Htbl[nlo]
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eor r4,r8,r4,lsr#4
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eor r4,r4,r5,lsl#28
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eor r5,r9,r5,lsr#4
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eor r5,r5,r6,lsl#28
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ldrh r8,[r2,r12] @ rem_4bit[rem]
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eor r6,r10,r6,lsr#4
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ldrbpl r12,[r0,r3]
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eor r6,r6,r7,lsl#28
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eor r7,r11,r7,lsr#4
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add r11,r1,r14
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and r14,r4,#0xf @ rem
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eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
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add r14,r14,r14
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ldmia r11,{r8-r11} @ load Htbl[nhi]
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eor r4,r8,r4,lsr#4
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eor r4,r4,r5,lsl#28
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eor r5,r9,r5,lsr#4
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ldrh r8,[r2,r14] @ rem_4bit[rem]
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eor r5,r5,r6,lsl#28
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eor r6,r10,r6,lsr#4
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eor r6,r6,r7,lsl#28
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eor r7,r11,r7,lsr#4
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andpl r14,r12,#0xf0
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andpl r12,r12,#0x0f
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eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
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bpl .Loop
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r4,r4
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str r4,[r0,#12]
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#elif defined(__ARMEB__)
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str r4,[r0,#12]
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#else
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mov r9,r4,lsr#8
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strb r4,[r0,#12+3]
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mov r10,r4,lsr#16
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strb r9,[r0,#12+2]
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mov r11,r4,lsr#24
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strb r10,[r0,#12+1]
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strb r11,[r0,#12]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r5,r5
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str r5,[r0,#8]
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#elif defined(__ARMEB__)
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str r5,[r0,#8]
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#else
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mov r9,r5,lsr#8
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strb r5,[r0,#8+3]
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mov r10,r5,lsr#16
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strb r9,[r0,#8+2]
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mov r11,r5,lsr#24
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strb r10,[r0,#8+1]
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strb r11,[r0,#8]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r6,r6
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str r6,[r0,#4]
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#elif defined(__ARMEB__)
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str r6,[r0,#4]
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#else
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mov r9,r6,lsr#8
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strb r6,[r0,#4+3]
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mov r10,r6,lsr#16
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strb r9,[r0,#4+2]
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mov r11,r6,lsr#24
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strb r10,[r0,#4+1]
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strb r11,[r0,#4]
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#endif
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#if __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev r7,r7
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str r7,[r0,#0]
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#elif defined(__ARMEB__)
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str r7,[r0,#0]
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#else
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mov r9,r7,lsr#8
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strb r7,[r0,#0+3]
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mov r10,r7,lsr#16
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strb r9,[r0,#0+2]
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mov r11,r7,lsr#24
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strb r10,[r0,#0+1]
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strb r11,[r0,#0]
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#endif
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r11,pc}
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#else
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ldmia sp!,{r4-r11,lr}
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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#endif
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.size gcm_gmult_4bit,.-gcm_gmult_4bit
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#if __ARM_ARCH__>=7 && !defined(__STRICT_ALIGNMENT)
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.fpu neon
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.global gcm_gmult_neon
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.type gcm_gmult_neon,%function
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.align 4
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gcm_gmult_neon:
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sub r1,#16 @ point at H in GCM128_CTX
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vld1.64 d29,[r0,:64]!@ load Xi
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vmov.i32 d5,#0xe1 @ our irreducible polynomial
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vld1.64 d28,[r0,:64]!
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vshr.u64 d5,#32
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vldmia r1,{d0-d1} @ load H
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veor q12,q12
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#ifdef __ARMEL__
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vrev64.8 q14,q14
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#endif
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veor q13,q13
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veor q11,q11
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mov r1,#16
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veor q10,q10
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mov r3,#16
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veor d2,d2
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vdup.8 d4,d28[0] @ broadcast lowest byte
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b .Linner_neon
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.size gcm_gmult_neon,.-gcm_gmult_neon
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.global gcm_ghash_neon
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.type gcm_ghash_neon,%function
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.align 4
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gcm_ghash_neon:
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vld1.64 d21,[r0,:64]! @ load Xi
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vmov.i32 d5,#0xe1 @ our irreducible polynomial
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vld1.64 d20,[r0,:64]!
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vshr.u64 d5,#32
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vldmia r0,{d0-d1} @ load H
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veor q12,q12
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nop
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#ifdef __ARMEL__
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vrev64.8 q10,q10
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#endif
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.Louter_neon:
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vld1.64 d29,[r2]! @ load inp
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veor q13,q13
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vld1.64 d28,[r2]!
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veor q11,q11
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mov r1,#16
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#ifdef __ARMEL__
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vrev64.8 q14,q14
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#endif
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veor d2,d2
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veor q14,q10 @ inp^=Xi
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veor q10,q10
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vdup.8 d4,d28[0] @ broadcast lowest byte
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.Linner_neon:
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subs r1,r1,#1
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vmull.p8 q9,d1,d4 @ H.lo<6C>Xi[i]
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vmull.p8 q8,d0,d4 @ H.hi<68>Xi[i]
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vext.8 q14,q12,#1 @ IN>>=8
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veor q10,q13 @ modulo-scheduled part
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vshl.i64 d22,#48
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vdup.8 d4,d28[0] @ broadcast lowest byte
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veor d3,d18,d20
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veor d21,d22
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vuzp.8 q9,q8
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vsli.8 d2,d3,#1 @ compose the "carry" byte
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vext.8 q10,q12,#1 @ Z>>=8
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vmull.p8 q11,d2,d5 @ "carry"<22>0xe1
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vshr.u8 d2,d3,#7 @ save Z's bottom bit
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vext.8 q13,q9,q12,#1 @ Qlo>>=8
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veor q10,q8
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bne .Linner_neon
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veor q10,q13 @ modulo-scheduled artefact
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vshl.i64 d22,#48
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veor d21,d22
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@ finalization, normalize Z:Zo
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vand d2,d5 @ suffices to mask the bit
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vshr.u64 d3,d20,#63
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vshl.i64 q10,#1
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subs r3,#16
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vorr q10,q1 @ Z=Z:Zo<<1
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bne .Louter_neon
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#ifdef __ARMEL__
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vrev64.8 q10,q10
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#endif
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sub r0,#16
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vst1.64 d21,[r0,:64]! @ write out Xi
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vst1.64 d20,[r0,:64]
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.word 0xe12fff1e
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.size gcm_ghash_neon,.-gcm_ghash_neon
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#endif
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.asciz "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
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.align 2
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#if defined(HAVE_GNU_STACK)
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.section .note.GNU-stack,"",%progbits
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#endif
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